{"id":40,"date":"2020-03-07T11:49:07","date_gmt":"2020-03-07T11:49:07","guid":{"rendered":"https:\/\/www.z88dx.com\/?page_id=40"},"modified":"2020-03-07T11:49:45","modified_gmt":"2020-03-07T11:49:45","slug":"z88-hardware-specification","status":"publish","type":"page","link":"https:\/\/www.z88dx.com\/index.php\/hardware\/z88-hardware-specification\/","title":{"rendered":"Z88 Hardware Specification"},"content":{"rendered":"\n<pre class=\"wp-block-preformatted\">\n References :\n\n1 - Z88 Service Manual - Issue 1, January 1985\n (Prepared by BRAVEMAY for Cambridge Computer Ltd.)\n2 - DMF690N Module Specification - 15\/07\/98\n (Prepared by OPTREX, Approved by Cambridge Computer Ltd.)\n\n Introduction\n The Z88 is organized around four integrated circuits: the Z80 \n microprocessor, a specialized gate-array called 'Blink', the ROM chip  \n and a pseudo-static RAM chip. There are 8 connectors on the \n motherboard: the expansion connector, the serial port, 2 for keyboard \n connections, one for the LCD and 3 for the slot connectors.\n\n We will describe here the pinout, the usage with modifications if possible.\n\n 1 - Integrated circuits\n This section will describe the four IC used in the Z88.\n IC1 : the Z80 CPU\n IC2 : the RAM\n IC3 : the ROM\n IC4 : the Blink\n An additional part is devoted to the Flash EPROMs.\n 1.1 - The Z80 CPU\n 1.1.1 - Version\n The microprocessor is a standard Z80 running in CMOS \n version for low working and standby power consumption.\n For Z88, 4MHz and 6MHz capable Z80 CMOS were used : Z84C004PSC or Z84C0006PSC.\n 1.1.2 - Pinout\n <code>  +--------------+<\/code>\n A11 |1    +--+   40| A10\n   A12 |2           39| A9\n   A13 |3           38| A8\n   A14 |4           37| A7\n   A15 |5           36| A6\n   CLK |6           35| A5\n    D4 |7           34| A4\n    D3 |8           33| A3\n    D5 |9           32| A2\n    D6 |10  Z84C00  31| A1\n   VCC |11    CPU   30| A0\n    D2 |12          29| GND\n    D7 |13          28| \/RFSH\n    D0 |14          27| \/M1\n    D1 |15          26| \/RST\n  \/INT |16          25| \/BUSRQ\n  \/NMI |17          24| \/WAIT\n \/HALT |18          23| \/BUSAK\n \/MREQ |19          22| \/WR\n \/IORQ |20          21| \/RD\n       +--------------+\n 1.1.3 - Clocks\n Two clocks are driving the Z80. MCK, the master clock and SCK, the standby clock.\n The MCK (3.2768 MHz) is generated by a 9.8304 Xtal to the Blink and divided by 3, given to the pin 6.\n The SCK pulses at 25.6 KHz and is active on COMA state.\n It is perhaps possible to overclock the Z80 if the Blink supports it!\n Actually, we can find up to 20MHz Z80 CMOS CPU. I think that 8MHz would be reasonable.\n But we must be sure that the LCD and the Blink will support these frequencies.\n (not until I got the Blink datasheets)\n There will probably be troubles with the Z88 clock\u2026 Interrupts will have to be rewritten\u2026\n 1.1.4 - Interrupts\n There are three pins for dealing with interruptions :\n BUSRQ (Bus Request) : used for DMA (not connected on the Z88)\n NMI (Non Maskable Interrupt) : Jumps to $0066 (BatLow, RTC\u2026)\n INT (Ordinary Interrupt) : used in mode 1 (IM1)\n For dealing with the maskable interruptions (INT), the Z80 can be switch in three modes.\n The interrupt mode 0 (IM0) : for 8080 compatibility\n The interrupt mode 1 (IM1) : for non-zilog environnemt (our case)\n The interrupt mode 2 (IM2) : for zilog environnement\n On reset, OZ puts the Z80 in IM1. \n If interrupts are enabled via an OZ_EI, every INT signal jumps to $0038.\n This routines deals with the keyboard, the bleep, the alarms\u2026\n 1.2 - The RAM\n 1.2.1 - RAM types\n The serial chip is a NEC uPD42832C. This is a 32K pseudo-static RAM \n chip. These chips are like dynamic RAM but have the ability to retain \n data under a standby voltage (around 2V) with a self refresh circuitry.\n   Dynamic RAM chip are incompatible. Static RAM chip can be use without \n any problem. The replacement is recommended because theyre power drain \n is very lowest (1\/10 ratio).\n 1.2.2 - RAM socket\n The motherboard layout has 32 pins. It is tracked for a 128K chip. On \n issue 4 machine a 32K chip is soldier using the 28 low pins.\n <code>  +--------------+<\/code>\n POE |1    +--+   32| VCC\n   A16 |2           31| A15\n   A14 |3           30| VCC\n   A12 |4           29| WE\n   A7  |5           28| A13\n   A6  |6           27| A8\n   A5  |7    Z88    26| A9\n   A4  |8    RAM    25| A11\n   A3  |9    PCB    24| POE\n   A2  |10          23| A10\n   A1  |11          22| CE\n   A0  |12          21| D7\n   D0  |13          20| D6\n   D1  |14          19| D5\n   D2  |15          18| D4\n   VSS |16          17| D3\n       +--------------+\n This table describes the 128K chip pinout and Blink signals.\n Pin    Chip    Blink   Pin Chip    Blink\n 1    POE POE 32  -   VCC\n 2    A16 MA16    31  A15 MA15\n 3    A14 MA14    30  [CS]    VCC\n 4    A12 MA12    29  [WE]    WRB\n 5    A7  MA7 28  A13 MA13\n 6    A6  MA6 27  A8  MA8\n 7    A5  MA5 26  A9  MA9\n 8    A4  MA4 25  A11 MA11\n 9    A3  MA3 24  [OE]    POE\n 10    A2  MA2 23  A10 MA10\n 11    A1  MA1 22  [CE]    IRCE (internal RAM chip enable)\n 12    A0  MA0 21  D7  MDH\n 13    D0  MDA 20  D6  MDG\n 14    D1  MDB 19  D5  MDF\n 15    D2  MDC 18  D4  MDE\n 16    VSS GND 17  D3  MDD\n 1.2.3 - Internal RAM upgrade\n It is easily possible to upgrade the internal RAM to 128K. For a 512K \n upgrade some hardware modification are needed. The OZ version 4 is the \n only one able to recognize a 512K internal upgrade.\n   For a 128K upgrade you can put a Toshiba TC551001 static RAM chip. It \n is very cheap (about \ufffd4). First, make a backup of your sensible files. \n Disassembly the box without batteries. Deconnect the two keyboard \n ribbons, the screen ribbon. Put your moterboard on a dry table without \n metal. Unsoldier the old chip. Soldier a 32 pins flat socket, Insert \n the new chip. You will have to cut some plastic structures (like an \n X) in the keyboard plastic support.\n For a 512K upgrade, you will have to wire the A17 and A18 pins with a \n link directly to address lines on a slot connector soldier. Only the OZ \n version 4 for UK is able to recognise an internal 512K upgrade.\n Replacing the old 42832 Rams will spare your battery life time. The \n slowest rams have less consumation (120 or 150 ns). For example :\n Size    Chip Type   Speed   Power (mW)  Manufacturer\n (K)        (ns)    Act\/Stdby\n 32K  (PS)    uPD42832C   -15L (150)  220 \/ 2.75  Nec\n 128K (S)    TC551001BPL -10L (100)  27.5\/ 0.02  Toshiba\n 512K (S)    TC554001BPL -70  (70)   50.0\/ 0.30  Toshiba\n 128K (PS)    TC518128PL  -12  (120)  275 \/ 0.55  Toshiba\n 512K (PS)    TC518512PL  -10  (100)  275 \/ 1.00  Toshiba\n 128K (PS)    HM658128ALP         Hitashi\n 512K (PS)    HM658512LP          Hitashi\n 512K (S)    HM628512LP          Hitashi\n (PS=Pseudo-static RAM chip, S=Static RAM chip)\n 1.3 - The ROM\n 1.3.1 - ROM types\n The serial rom chip is an UV eprom NEC uPD23C1000C for foreign OZ. \n The UK version may be an eprom chip for v2.2, the v3.0 supports exactly \n the same software but have been put in a ROM which have only 28 pins. \n The last v4.0 is fitted on an EPROM chip. The socket layout isn't \n standard according to the NEC standard (see below). If you wish to fit \n a new eprom, be very careful, pins 2 and 24 must be exchanged according \n to the JEDEC standard. Particulary if you want to use actual 128K Eprom \n chip, like 27C1001. In theory, you can fit larger eprom (like 27C2000 \n or 27C4000) if you wire the addresses lines.\n 1.3.2 - ROM socket\n The mother has 32 pins tracked to the NEC standard.\n <code>  +--------------+<\/code>\n VCC |1    +--+   32| VCC\n   ROE |2           31| VCC\n   A15 |3           30| VCC\n   A12 |4           29| A14\n   A7  |5           28| A13\n   A6  |6           27| A8\n   A5  |7    Z88    26| A9\n   A4  |8    ROM    25| A11\n   A3  |9    PCB    24| A16\n   A2  |10          23| A10\n   A1  |11          22| CE\n   A0  |12          21| D7\n   D0  |13          20| D6\n   D1  |14          19| D5\n   D2  |15          18| D4\n   VSS |16          17| D3\n       +--------------+\n This table describes the 128K chip pinout and Blink signals.\n Pin    Chip    Blink   Pin Chip    Blink\n 1    VPP VCC 32  VCC VCC\n 2    [OE]    ROE 31  [PGM]   VCC\n 3    A15 MA15    30  VCC VCC\n 4    A12 MA12    29  A14 MA14\n 5    A7  MA7 28  A13 MA13\n 6    A6  MA6 27  A8  MA8\n 7    A5  MA5 26  A9  MA9\n 8    A4  MA4 25  A11 MA11\n 9    A3  MA3 24  A16 MA16\n 10    A2  MA2 23  A10 MA10\n 11    A1  MA1 22  [CE]    IPCE (Internal PROM chip enable)\n 12    A0  MA0 21  D7  MDH\n 13    D0  MDA 20  D6  MDG\n 14    D1  MDB 19  D5  MDF\n 15    D2  MDC 18  D4  MDE\n 16    VSS GND 17  D3  MDD\n 1.4 - The BLINK gate array\n This private chip is a NEC uPD65031. It is CMS soldiered on the \n PCB. It manages the memory bank switching, the LCD, the serial port, \n the interrupts\u2026\n It is the heart of the machine. Actually we just know \n its pinout and the description of some registers. The conceptors have \n lost the original notes\u2026\n Pin    Chip    Z80 Pin Chip\n 1    GND     52  VDD\n 2    VDD     53  GND\n 3    IOR [IORQ]  54  MA16\n 4    CRD [RD]    55  MA15\n 5    MRQ [MREQ]  56  MA14\n 6    HLT [HALT]  57  MA12\n 7    NMIB    [NMI]   58  MA7\n 8    INTB    [INT]   59  MA13\n 9    CDB D1  60  MA6\n 10    ROUT    [RST]   61  MA8\n 11    CDA D0  62  MA5\n 12    CMI [MI]    63  WRB\n 13    CDH D7  64  MA9\n 14    CDC D2  65  MA4\n 15    CA0 A0  66  MA11\n 16    CDG D6  67  MA3\n 17    CA1 A1  68  IPCE    (ROM.0 CE) \n 18    CDF D5  69  MA2\n 19    CA2 A2  70  MA10\n 20    CDD D3  71  MA1\n 21    CA3 A3  72  MA0\n 22    CDE D4  73  MDH\n 23    CA4 A4  74  MDA\n 24    CA5 A5  75  MDG\n 25    CA15    A15 76  MDB\n 26    CA6 A6  77  MDF\n 27    CA14    A14 78  MDC\n 28    GND     79  VDD\n 29    VDD     80  GND\n 30    CA13    A13 81  MDE\n 31    CA7 A7  82  MDD\n 32    CA8 A8  83  MA17\n 33    CA12    A12 84  MA18\n 34    CA9 A9  85  MAW(19)\n 35    CA11    A11 86  SE1 (slot1 CE)\n 36    CA10    A10 87  POE\n 37    TxD (serial)    88  ROE\n 38    RCS (serial)    89  PGMB    (PGM low)\n 39    IRCE    (RAM.0 CE)  90  EOE\n 40    GND     91  SE3 (slot3 CE)\n 41    RxD (serial)    92  FLP (flap)\n 42    CTS (serial)    93  SE2 (slot2 CE)\n 43    DCD (serial)    94  SNS (sens line)\n 44    PN1 (display)   95  VPON    (VPP on)\n 45    LD  (display)   96  BTL (Batt low)\n 46    FR  (display)   97  RIN\n 47    XSCL    (display)   98  MCK\n 48    LD0 (display)   99  SCK\n 49    LD1 (display)   100 SPKR    (speaker)\n 50    LD2 (display)\n 51    LD3 (display)\n 1.5 - The Flash Eproms\n The new Flash Eprom cards represent a new way for Z88 storage. Its \n main feature is an integrated electrical erasure. The prototype cards \n are built with an Intel 28F008SA and the serial cards uses the Intel \n 28F008S5 (which is fastest). Theyre low relative cost make them the new \n media for 1 Megabyte application card and file storage.\n   They have 44 pins in a PSOP format (0.5 mm between each pin). They \n are linked to the slot connector like standard eproms.\n <code>  +--------------+<\/code>\n VPP |1    +--+   44| VCC\n   RP# |2           43| -\n   A11 |3           42| A12\n   A10 |4           41| A13\n   A9  |5           40| A14\n   A8  |6           39| A15\n   A7  |7           38| A16\n   A6  |8           37| A17\n   A5  |9           36| A18\n   A4  |10          35| A19\n |11  Intel   34| -\n |12  28F008  33| -\n A3  |13  SA\/S5   32| -\n A2  |14          31| -\n A1  |15          30| WE#\n A0  |16          29| OE#\n D0  |17          28| -\n D1  |18          27| D7\n D2  |19          26| D6\n D3  |20          25| D5\n GND |21          24| D4\n GND |22          23| VCC\n   +--------------+ \n The table below describes the links between the edge connector and the chip.\n Slot signal    Flash Signal\n 1  MA16        A16 38\n 2  MA15        A15 39\n 3  MA12        A12 42\n 4  MA7        A7  7\n 5  MA6        A6  8\n 6  MA5        A5  9\n 7  MA4        A4  10\n 8  MA3        A3  13\n 9  MA2        A2  14\n 10 MA1        A1  15\n 11 MA0        A0  16\n 12 MDA        D0  17\n 13 MDB        D1  18\n 14 MDC        D2  19\n 15 SNS\n 16 GND        GND 21\n 17 GND        GND 22\n 18 MA14        A14 40\n 19 VPP        VPP 1\n 20 VCC        VCC 44,23\n 21 VCC        -\n 22 PGM        WE# 30\n 23 MA13        A13 41\n 24 MA8        A8  6\n 25 MA9        A9  5\n 26 MA11        A11 3\n 27 POE        -\n 28 EOE        OE# 29\n 29 MA10        A10 4\n 30 SE3        CE# 43\n 31 MDH        D7  27\n 32 MDG        D6  26\n 33 MDD        D3  20\n 34 MDE        D4  24\n 35 MDF        D5  25\n 36 MA17        A17 37\n 37 MA18        A18 36\n 38 MA19        A19 35\n Other pins:\n Pin 1 : Vpp\n Pin 23: Vcc\n Pin 44: Vcc\n Must be connected to a 100nF ceramic capacitor.\n Pin 2 : RP# connected to VCC\n NB: all the VCC and GND pins have to be connected.\n 2 - The Connectors\n 2.1 - SLOT connectors\n It is private format connector wiring 38 pins. They are devoted for \n memory addressing. Each slot is able to address 1024K. The slot 3 \n present a Vpp (12V) line, useful for Eprom programming. Pseudo-static \n RAM, static RAM, EPROM and Flash EPROM can be used.\n Slot    RAM\/ROM RAM\/ROM Eprom   Pins for    Pins for    Pins for\n pins    Slot 1  Slot 2  Slot 3  32K 128K    32K \n     Signals Signals Signals EPROM   EPROM   RAM\n 1    A16 A16 A16 -   24  -\n    2    A15 A15 A15 -   3   -\n    3    A12 A12 A12 2   4   2\n    4    A7  A7  A7  3   5   3\n    5    A6  A6  A6  4   6   4\n    6    A5  A5  A5  5   7   5\n    7    A4  A4  A4  6   8   6\n    8    A3  A3  A3  7   9   7\n    9    A2  A2  A2  8   10  8\n   10    A1  A1  A1  9   11  9\n   11    A0  A0  A0  10  12  10\n   12    D0  D0  D0  11  13  11\n   13    D1  D1  D1  12  14  12\n   14    D2  D2  D2  13  15  13\n   15    SNSL    SNSL    SNSL    -   -   -\n   16    GND GND GND 14  16  14\n   17    GND GND GND 14  16  14\n   18    A14 A14 A14 27  29  1\n   19    VCC VCC VPP 1   1   -\n   20    VCC VCC VCC 28  32  -\n   21    VCC VCC VCC -   -   28\n   22    WEL WEL PGML    -   31  -\n   23    A13 A13 A13 26  28  26\n   24    A8  A8  A8  25  27  25\n   25    A9  A9  A9  24  26  24\n   26    A11 A11 A11 23  25  23\n   27    POE POE POE -   -   22\n   28    ROE ROE EOE 22  2   -\n   29    A10 A10 A10 21  23  21\n   30    SE1 SE2 SE3 20  22  20\n   31    D7  D7  D7  19  21  19\n   32    D6  D6  D6  18  20  18\n   33    D3  D3  D3  15  17  15\n   34    D4  D4  D4  16  18  16\n   35    D5  D5  D5  17  19  17\n   36    A17 A17 A17 -   -   -\n   37    A18 A18 A18 -   -   -\n   38    A19 A19 A19 -   -   -\n 2.2 - The expansion port connector\n It is a standard 2.54mm double sided 48 pins male connector for \n expansion. It presents all the Z80 bus signals. On the issue 4 version, \n the flap has been sealed because expansion insertion may result in a \n crash due to static electricity.\n <code>Component       P C B Side A  Edge    Side B  GND 1   SNSL    see below A11 2   +12v A12 3   A10 A13 4   A9 A14 5   A8 A15 6   A7 clock   7   A6 D4  8   A5 D3  9   A4 D5  10  A3 D6  11  A2 VCC 12  A1 D2  13  A0 GND 14  GND D0  15  D7 D1  16  M1L INTL    17  FLP     (flap switch) slot    18  slot HALTL   19  NMIL MREQL   20  WRL IORQL   21  RDL MAWL    22  RESETL  Resets Z88 (2 pulses required) -BT 23  SVCC    5.4v while the machine is 'on.' GND 24  SNSL <\/code>\n SNSL allows the machine to be automaticly placed into comotose state \n buy causing a 'power fail interupt' when an edge connector is plugged \n into to the expansion slot of the Z88.\n 2.3 - The Serial Port Connector\n This is a DB9 male connector with a private pinout describe below.\n Pin    Signal          Sens\n 1 -     unswitched  +5v at 10 uA            output\n 2 TxD      transmit data           output\n 3 RxD     receive data            input\n 4 RTS     ready to send           output \n 5 CTS     clear to send           input\n 6 -         reserved for future use\n 7 GND\n 8 DCD    data carrier detect         input\n 9 DTR    switched +5v  at 1mA            output\n Note : DTR is high when the machine is awake. The machine is always \n awake when the screen is active, but even if asleep the machine will \n wake every minute or so to carry out various housekeeping tasks, such \n as checking for alarms, and at these time DTR will go high. Pin 1 will \n show a signal if there is power available to the machine.\n The PC DB9 female connector\n 1 DCD\n 2 RxD\n 3 TxD\n 4 DTR\n 5 GND\n 6 DSR\n 7 RTS\n 8 CTS\n 9 -\n The PC link cable\n Z88    PC  Z88 (front view)        PC (front view)\n     1 - 4\n 2 ---------    2   1 2 3 4 5       5 4 3 2 1\n 3 ---------    3    6 7 8 9         9 8 7 6\n 4 ---------    8\n 5 ---------    7\n 7 ---------    5\n 8 - 9\n 2.4 - The keyboard connectors\n The keyboard is just 8 * 8 matrix between the Z80 address and data \n buses. It is connected on SK6 and SK7. In theory it is possible to \n replace the membrane by a PCB with mechanical keys (and resistors in \n serial). The rubber keyboard technology seems to consume a lot of \n power.\n SK6 signals        SK7 signals\n 1    A14     1   D5\n 2    A15     2   D4\n 3    A13     3   D3\n 4    A12     4   D1\n 5    A11     5   D7\n 6    A10     6   D0\n 7    A9      7   D6\n 8    A8      8   D2\n Keyboard matrix (for the QWERTY UK)\n A15 A14 A13 A12 A11 A10 A09 A08\n 2   1   3   4   5   6   7   8\n RSH HLP [   ]   -   =   \\   DEL    5   D7\n SQR LSH SPC LFT RGT DWN UP  ENT    7   D6\n ESC TAB 1   2   3   4   5   6      1   D5\n INX DIA Q   W   E   R   T   Y      2   D4\n CAP MEN A   S   D   F   G   H      3   D3\n .   ,   Z   X   C   V   B   N      8   D2\n \/   ;   L   M   K   J   U   7      4   D1\n \ufffd   \"   0   P   9   O   I   8      6   D0\n There are two issues for the keyboard membrane : a red one, the \n first, and the green one which is the last and the most common. The \n first issue (red) seems to be often unreliable with a lot of short \n circuits which sends a lot of unexpected characters\u2026 It is impossible \n to repair them. The green issues are very good. I have got mine since \n ten years and I am actually typing on it\u2026\n The keyboard is probably the only part with which you encountered \n troubles. You can keep the same for all your life if you think to clean \n the contacts sometimes. After a long time, some carbon particle \n agglomerate on the membrane and generate short-circuits. The \n only thing to do is to clean the contact surfaces with some \n alcohol. Unscrew the case, deconnect the keyboard ribbons. Pull out the \n rubber and be very careful of the three slot. Clean all the keys \n surfaces on the rubber and the membrane with a tissue with a few \n standard alcohol (90\ufffd). Dry it before reassembling. Do it carefully \n especially on the cursor, tab, diamond, square, enter and shift keys. \n 2.5 - The LCD connector\n The most common LCD module is the DMF690N produced by OPTREX. \n Some previous versions exist, with more failure and less contrast.\n This unit has its own PCB.\n The LCD panel is a dot matrix of 640*64 pixels, the NRD7482.\n It is driven by nine CMS chips.\n One SED1610 : a 86 lines driver and eight SED1600 : 80 rows dirvers.\n Another IC is devoted to voltage generation.\n The module is connected by a special ribbon with 14 links on SK5.\n Ribbon signals:\n 14 is the left one, 1 is on the right in top view.\n Pin    Symbol  Level   Function\n 1    VDD -   Base supply (0V)\n 2    VSS -   Power supply for Logic\n 3    VLCD    -   Power supply for LCD driving\n 4    LP  H>L Date Latch signal\n 5    FR  H\/L Alternate signal for LCD driving\n 6    YDIS    L   Display off signal\n 7    NC  -   No connection\n 8    DIN H   Frame signal\n 9    XSCL    H>L Clock signal for shifting serial data\n 10    NC  -   No connection\n 11    D0  H\/L Display data\n 12    D1  H\/L Display data\n 13    D2  H\/L Display data\n 14    D3  H\/L Display data\n All of these signals are directly managed by the blink. It builts the screen by\n reading directly in the memory the different character set and screen base.\n The cursor is hardware managed too.\n Conclusion\n There is still a lot of thinks to do to improve the Z88 hardware:\n IR serial interface\n mechanical keyboard\n overclocked Z80 CPU\n small integrated supply with NiMH battery charger\n video interface\n A\/D and D\/A converter interface<\/pre>\n","protected":false},"excerpt":{"rendered":"<p>References : 1 &#8211; Z88 Service Manual &#8211; Issue 1, January 1985 (Prepared by BRAVEMAY for Cambridge Computer Ltd.) 2 &#8211; DMF690N Module Specification &#8211; [&#8230;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":33,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-40","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/pages\/40","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/comments?post=40"}],"version-history":[{"count":0,"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/pages\/40\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/pages\/33"}],"wp:attachment":[{"href":"https:\/\/www.z88dx.com\/index.php\/wp-json\/wp\/v2\/media?parent=40"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}